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  rev.2.00, oct.30. 2003, page 1 of 9 H7N1002AB silicon n channel mos fet high speed power switching rej03g0130-0200z rev.2.00 oct.30.2003 features ? low on-resistance r ds(on) = 8 m ? typ. ? low drive current ? available for 4.5 v gate drive outline to-220ab 1 2 3 1. gate 2. drain (flange) 3. source d g s
H7N1002AB rev.2.00, oct.30. 2003, page 2 of 9 absolute maximum ratings (ta = 25c) item symbol ratings unit drain to source voltage v dss 100 v gate to source voltage v gss 20 v drain current i d 75 a drain peak current i d(pulse) note1 300 a body-drain diode reverse drain current i dr 75 a avalanche current i ap note3 50 a avalanche energy e ar note3 166 mj channel dissipation pch note2 100 w channel temperature tch 150 c storage temperature tstg ?55 to +150 c notes: 1. pw 10 s, duty cycle 1 % 2. value at tc = 25 c 3. value at tch = 25 c, rg 50 ?
H7N1002AB rev.2.00, oct.30. 2003, page 3 of 9 electrical characteristics (ta = 25c) item symbol min typ max unit test conditions drain to source breakdown voltage v (br)dss 100 ? ? v i d = 10 ma, v gs = 0 gate to source breakdown voltage v (br)gss 20 ? ? v i g = 100 a, v ds = 0 gate to source leak current i gss ??10 av gs = 16 v, v ds = 0 zero gate voltage drain current i dss ??10 av ds = 100 v, v gs = 0 gate to source cutoff voltage v gs(off) 1.5 ? 2.5 v i d = 1 ma, v ds = 10 v note1 static drain to source on state r ds(on) ?8 10m ? i d = 37.5 a, v gs = 10 v note1 resistance ? 10 15 m ? i d = 37.5 a, v gs = 4.5 v note1 forward transfer admittance |y fs | 5795? s i d = 37.5 a, v ds = 10 v note1 input capacitance ciss ? 9700 ? pf v ds = 10 v output capacitance coss ? 740 ? pf v gs = 0 reverse transfer capacitance crss ? 330 ? pf f = 1 mhz total gate charge qg ? 155 ? nc v dd = 50 v gate to source charge qgs ? 35 ? nc v gs = 10 v gate to drain charge qgd ? 33 ? nc i d = 75 a turn-on delay time t d(on) ?43?nsv gs = 10 v, i d = 37.5 a rise time t r ? 245 ? ns r l = 0.8 ? turn-off delay time t d(off) ? 130 ? ns r g = 4.7 ? fall time t f ?25?ns body?drain diode forward voltage v df ?0.93?v i f = 75 a, v gs = 0 body?drain diode reverse recovery time t rr ?70?nsi f = 75 a, v gs = 0 dif/ dt = 100 a/ s notes: 1. pulse test
H7N1002AB rev.2.00, oct.30. 2003, page 4 of 9 main characteristics 30 10 3 1 0.3 0.1 0.1 0.3 1 3 10 30 100 50 40 30 20 10 0 2 46810 50 40 30 20 10 0 1 5 0.03 100 ta = 25 c 10 v v gs = 3 v 3.4 v tc = 75 c 25 c -25 c drain to source voltage v ds (v) drain current i d (a) maximum safe operation area drain to source voltage v ds (v) drain current i d (a) typical output characteristics pulse test gate to source voltage v gs (v) drain current i d (a) typical transfer characteristics v ds = 10 v pulse test 100 s 1 ms pw = 10 ms (1shot) dc opera tion (tc = 25 c) 10 s 4 v 3.6 v operation in this area is limited by r ds(on) 2 34 200 150 100 50 0 50 100 150 200 channel dissipation pch (w) case temperature tc ( c) power vs. temperature derating 300
H7N1002AB rev.2.00, oct.30. 2003, page 5 of 9 200 5 20 100 21050 5 10 20 50 1 2 0.5 0.01 100 10 100 10 0.1 1 0.02 0.1 1 static drain to source on state resistance vs. drain current 25 c tc = ?25 c 75 c v ds = 10 v pulse test drain current i d (a) static drain to source on state resistance r ds(on) (m ? ) pulse test static drain to source on state resistance vs. temperature forward transfer admittance vs. drain current case temperature tc ( c) drain current i d (a) static drain to source on state resistance r ds(on) (m ? ) forward transfer admittance |yfs| (s) v gs = 4.5 v 10 v 0.8 0.6 0.4 0.2 0 5 101520 drain to source saturation voltage vs. gate to source voltage 1.0 i d = 50 a 20 a 10 a pulse test gate to source voltage v gs (v) drain to source saturation voltage v ds(on) (v) 40 32 24 16 8 -40 0 40 80 120 160 0 i d = 10 a, 20 a 10 a, 20 a v gs = 4.5 v 10 v pulse test 50 a 50 a 200
H7N1002AB rev.2.00, oct.30. 2003, page 6 of 9 01020304050 2000 5000 10000 1000 100 200 500 200 160 120 80 40 0 20 16 12 8 4 80 160 240 320 400 0 1000 100 1 10 0.1 0.3 1 3 10 30 100 20 50 20000 v gs = 0 f = 1 mhz ciss coss crss i d = 75 a v ds v gs v dd = 25 v 50 v 80 v v dd = 80 v 50 v 25 v r t d(on) t d(off) t t f v gs = 10 v, v dd = 30 v pw = 5 s, duty 1% r g = 4.7 ? typical capacitance vs. drain to source voltage capacitance c (pf) drain to source voltage v ds (v) dynamic input characteristics switching characteristics drain to source voltage v ds (v) gate to source voltage v gs (v) switching time t (ns) gate charge qg (nc) drain current i d (a) body-drain diode reverse recovery time reverse recovery time trr (ns) reverse drain current i dr (a) 0.1 0.3 1 3 10 30 100 1000 100 20 50 200 500 10 di / dt = 100 a / s v gs = 0, ta = 25 c
H7N1002AB rev.2.00, oct.30. 2003, page 7 of 9 d. u. t rg i monitor ap v monitor ds v dd 50 ? vin 15 v 0 i d v ds i ap v (br)dss l v dd e =  l  i  2 1 v v ? v ar ap dss dss dd 2 200 160 120 80 40 25 50 75 100 125 150 0 i ap = 50 a v dd = 25 v duty < 0.1 % rg > 50 ? channel temperature tch ( c) repetitive avalanche energy e ar (mj) maximum avalanche energy vs. channel temperature derating avalanche test circuit avalanche waveform 0 0.4 0.8 1.2 1.6 2.0 100 80 60 40 20 v gs = 10 v 5 v pulse test 0, ?5 v reverses drain current vs. source to drain voltage reverse drain current i dr (a) source drain voltage v sd (v)
H7N1002AB rev.2.00, oct.30. 2003, page 8 of 9 vin monitor d.u.t. vin 10 v r l v = 30 v ds tr td(on) vin 90% 90% 10% 10% vout td(off) vout monitor 90% 10% t f switching time test circuit switching time waveform rg normalized transient thermal impedance vs. pulse width pulse width pw (s) normalized transient thermal impedance s (t) 3 1 0.3 0.1 0.03 0.01 10 100 1 m 10 m 100 m 1 10 tc = 25 c d = 1 0.5 0.2 0.1 0.05 0.02 0.01 1shot p ulse dm p pw t d = pw t ch - c(t) = s (t) ? ch - c ch - c = 1.25 c/ w, tc = 25 c
H7N1002AB rev.2.00, oct.30. 2003, page 9 of 9 package dimensions 0.5 0.1 2.54 0.5 0.76 0.1 14.0 0.5 15.0 0.3 2.79 0.2 18.5 0.5 7.8 0.5 10.16 0.2 2.54 0.5 1.26 0.15 4.44 0.2 2.7 max 1.5 max 11.5 max 9.5 8.0 1.27 6.4 +0.2 ?0.1 3.6 +0.1 ?0.08 package code jedec jeita mass (reference value) to-220ab conforms conforms 1.8 g as of january, 2003 unit: mm
? 2003. renesas technolo gy corp., all ri g hts reserved. printed in japan . colo p hon 1.0 keep safet y first in y our circuit desi g ns ! 1. renesas technolo gy corp. puts the maximum effort into makin g semiconductor products better and more reliable, but there is alwa y s the possibilit y that trouble m a y occur with them. trouble with semiconductors ma y lead to personal in j ur y , fire or propert y dama g e . remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placem ent of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. notes regarding these materials 1. these materials are intended as a reference to assist our customers in the selection of the renesas technology corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to renesas t echnology corp. or a third party. 2. renesas technology corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. all information contained in these materials, including product data, diagrams, charts, programs and algorithms represents i nformation on products at the time of publication of these materials, and are subject to change by renesas technology corp. without notice due to product improvement s or other reasons. it is therefore recommended that customers contact renesas technology corp. or an authorized renesas technology corp. product distrib utor for the latest product information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. renesas technology corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. please also pay attention to information published by renesas technology corp. by various means, including the renesas tech nology corp. semiconductor home page (http://www.renesas.com). 4. when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, a nd algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. renesas technology corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. renesas technology corp. semiconductors are not designed or manufactured for use in a device or system that is used under ci rcumstances in which human life is potentially at stake. please contact renesas technology corp. or an authorized renesas technology corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerosp ace, nuclear, or undersea repeater use. 6. the prior written approval of renesas technolo gy corp. is necessar y to reprint or reproduce in whole or in part these materials . 7 . if these products or technolo g ies are sub j ect to the japanese export control restrictions, the y must be exported under a license from the japanese g overnment and cannot b e imported into a countr y other than the approved destination. an y diversion or reexport contrar y to the export control laws and re g ulatio n s of japan and/or the countr y of destination is prohibited . 8. please contact renesas technolo gy corp. for further details on these materials or the products contained therein . s ales strate g ic plannin g div. nippon bld g ., 2-6-2, ohte-machi, chi y oda-ku, tok y o 100-0004, japa n htt p ://www.renesas.co m renesas technology america, inc. 450 holger way, san jose, ca 95134-1368, u.s.a tel: <1> (408) 382-7500 fax: <1> (408) 382-7501 renesas technology europe limited. dukes meadow, millboard road, bourne end, buckinghamshire, sl8 5fh, united kingdom tel: <44> (1628) 585 100, fax: <44> (1628) 585 900 renesas technology europe gmbh dornacher str. 3, d-85622 feldkirchen, germany tel: <49> (89) 380 70 0, fax: <49> (89) 929 30 11 renesas technology hong kong ltd. 7/f., north tower, world finance centre, harbour city, canton road, hong kong tel: <852> 2265-6688, fax: <852> 2375-6836 renesas technology taiwan co., ltd. fl 10, #99, fu-hsing n. rd., taipei, taiwan tel: <886> (2) 2715-2888, fax: <886> (2) 2713-2999 renesas technology (shanghai) co., ltd. 26/f., ruijin building, no.205 maoming road (s), shanghai 200020, china tel: <86> (21) 6472-1001, fax: <86> (21) 6415-2952 renesas technology singapore pte. ltd. 1, harbour front avenue, #06-10, keppel bay tower, singapore 098632 tel: <65> 6213-0200, fax: <65> 6278-8001 renesas sales offices


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